1. Field of the Invention
Embodiments of the present invention relate generally to a semiconductor memory device. More particularly, embodiments of the invention relate to a flash memory device having multi-bit memory cells.
This application claims the priority of Korean Patent Application No. 2005-78372, filed Aug. 25, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Flash memory is a popular form of non-volatile memory used in many modern electronic devices. Functionally, flash memory is a type of electrically erasable programmable read only memory (EEPROM) where memory cells can be programmed or read individually, but must be erased in units called “blocks.” Flash memory can be found in a wide range of consumer and industrial electronic devices, from personal computers (PCs) and removable disk drives to cameras, cellular phones, and personal digital assistants.
Among the reasons for flash memory's popularity are its high degree of integration, high performance, durability, low power consumption, and its ability to store data even when power is cut off. Some of flash memory's drawbacks include its tendency to wear out over time (lack of endurance), the inability to erase one memory cell at a time, and its relatively low degree of integration and speed compared with various forms of volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM).
The memory cells of a flash memory device are similar to traditional metal-oxide semiconductor (MOS) transistors, except that flash memory cells have two gate structures: a control gate and a floating gate. The floating gate is typically located between the control gate and a channel region and surrounded by an insulating layer such as an oxide layer. Data is stored in a flash memory cell by transferring electrical charges to the cell's floating gate during a programming operation. The data can then be read from the memory cell by applying a predetermined read voltage to the cell's control gate in a read operation and determining whether current can flow through the channel region. As more electrical charges are stored in the cell's floating gate, the amount of current that can flow through the channel decreases accordingly, because the stored electrical charges effectively raise the “threshold voltage” required to turn the cell on. Accordingly, a logic state of the memory cell can be determined by an amount of current that flows through the memory cell during the read operation.
The memory cells in most flash memory devices only store one bit of information. However, some flash memory devices use multi-bit memory cells which can store more than one bit. Similar to a one-bit flash memory cell, a multi-bit memory cell typically stores data by transferring discrete amounts of electrical charges to the cell's floating gate so that the cell's threshold voltage will fall into one of multiple predefined strata; the multi-bit memory cell reads the data by applying different read voltages to the memory cell's control gate and measuring whether current flows through the cell's channel region when the different read voltages are applied.
For example, FIGS. 1 and 2 illustrate a method for performing a read operation to detect the logic state of a 2-bit flash memory cell. Referring to FIGS. 1 and 2, a first read voltage VREAD_L is applied to a selected word line during a first read period RD1; a second read voltage VREAD_M is applied to a selected word line in a second read period RD2; and a third read voltage VREAD_H is applied to a selected word line in a third read period RD3. In other words, the word line voltage gradually increases from first read voltage VREAD_L to third read voltage VREAD_H during the read operation.
If current flows through the memory cell when first read voltage VREAD_L is applied to the cell through the selected word line, then the memory cell stores “11.” Else, if current flows through the memory cell when second read voltage VREAD_M is applied to the cell through the selected word line, then the memory cell stores “10.” Else, if current flows through the memory cell when third read voltage VREAD_H is applied to the cell through the selected wordline, then memory cell stores “01.” Otherwise, if current never flows through the memory cell during the first through third read periods, the memory cell stores “00.”
Read voltages VREAD_L, VREAD_M and VREAD_H are typically generated using a conventional high-voltage generating circuit and supplied to selected word lines WLi through a transmission path during respective first through third read periods RD1 through RD3. The time required to set the read voltage on a particular selected word line WLi to a required voltage level, which is called a develop time (labeled “td” in FIG. 2), depends on the resistive-capacitive (RC) load of the transmission path. Where the transmission path is long, the develop time tends to increase accordingly.
Compared with a read operation for a 1-bit flash memory cell, a read operation for a multi-bit flash memory cell is slower due to the three read periods. Moreover, the develop time also tends to increase the time required for the read operation of the multi-bit cell. In other words, as the develop time becomes longer, the read time of the multi-bit cell increases accordingly. As a result, the read performance of the multi-bit cell is degraded.